Re: [PATCH] Documentation: devicetree: mct: Fix counter bit of CPUlocal timers

From: Jingoo Han
Date: Wed Jan 22 2014 - 03:09:14 EST

On Tuesday, January 21, 2014 6:03 PM, Jingoo Han wrote:
> According to the datasheet of Exynos SoCs, the counter bit
> of CPU local timers is 31-bit, not 32-bit; thus, it should
> be fixed.

Please, ignore this patch.
There is a 31-bit counter in CPU local timers; however,
FRC (free running down-counters) of CPU local timers is
32-bit. Thus, there is no need to fix it.
Thank you.

Best regards,
Jingoo Han

> Signed-off-by: Jingoo Han <jg1.han@xxxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> index 167d5da..8c77791 100644
> --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> @@ -3,7 +3,7 @@ Samsung's Multi Core Timer (MCT)
> The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
> global timer and CPU local timers. The global timer is a 64-bit free running
> up-counter and can generate 4 interrupts when the counter reaches one of the
> -four preset counter values. The CPU local timers are 32-bit free running
> +four preset counter values. The CPU local timers are 31-bit free running
> down-counters and generate an interrupt when the counter expires. There is
> one CPU local timer instantiated in MCT for every CPU in the system.
> --

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