x86: Inconsistent xAPIC synchronization in arch_irq_work_raise?

From: Jan Kiszka
Date: Tue Jan 21 2014 - 08:28:44 EST

Hi all,

while trying to plug a race in the CPU hotplug code on xAPIC systems, I
was analyzing IPI transmission patterns. The handlers in
arch/x86/include/asm/ipi.h first wait for ICR, then send. In contrast,
arch_irq_work_raise sends the self-IPI directly and then waits. This
looks inconsistent. Is it intended?

BTW, the races are in wakeup_secondary_cpu_via_init and
wakeup_secondary_cpu_via_nmi (lacking IRQ disable around ICR accesses).
There we also send first, then wait for completion. But I guess that is
due to the code originally only being used during boot. Will send fixes
for those once the sync pattern is clear to me.


Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux
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