Re: [PATCH/RFC] spi: core: Fix logic mismatch in spi_master.set_cs()

[Geert Uytterhoeven]

Hi Mark,

On Tue, Jan 14, 2014 at 1:52 PM, Mark Brown <broonie@xxxxxxxxxx> wrote:
>On Tue, Jan 14, 2014 at 12:36:51PM +0100, Geert Uytterhoeven wrote:
>
>> The documentation for spi_master.set_cs() says:
>>
>>     assert or deassert chip select, true to assert
>>
>> i.e. its "enable" parameter uses assertion-level logic.

>> For SPI controller-based chip selects, active high chip selects must be
>> handled by the SPI master driver, if supported (some SPI controllers have
>> configurable chip select polarity).
>
> This also pushes the handling of CS_HIGH back out into the driver which
> doesn't seem like it's helping anything.  Flipping the sense of enable

It depends: on hardware with separate register bits for chip select polarity
and chip select assertion it avoids having to invert the enable value a second
time.

> when calling set_cs() is probably OK though.

Just flipping the sense of enable still needs a documentation update.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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