[PATCH 4/7] clk: highbank: prevent glitching when going into bypass mode

[Rob Herring]

From: Mark Langsdorf <mark.langsdorf@xxxxxxxxxxx>

Under very rare circumstances, the clock multiplexer can take around
100 ns to enter bypass mode. Attempting to reprogram the clock PLL
before the clock has fully entered bypass mode can cause errors in the
system, up to and including kernel panics. Add a 300 ns delay after
programming the bypass enable to make sure that bypass mode has been
enabled.

This patch should be added to the stable series.

Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxxxxxx>
Cc: Mike Turquette <mturquette@xxxxxxxxxx>
Signed-off-by: Rob Herring <rob.herring@xxxxxxxxxxx>
---
 drivers/clk/clk-highbank.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index 2e7e9d9..dc7ca30 100644
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -21,6 +21,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/delay.h>
 
 #define HB_PLL_LOCK_500		0x20000000
 #define HB_PLL_LOCK		0x10000000
@@ -167,6 +168,8 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
 		/* Need to re-lock PLL, so put it into bypass mode */
 		reg |= HB_PLL_EXT_BYPASS;
 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
+		/* delay to make sure we are in bypass */
+		ndelay(300);
 
 		writel(reg | HB_PLL_RESET, hbclk->reg);
 		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
@@ -182,6 +185,9 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
 		reg &= ~HB_PLL_EXT_BYPASS;
 	} else {
 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
+		/* delay to make sure we are in bypass */
+		ndelay(300);
+
 		reg &= ~HB_PLL_DIVQ_MASK;
 		reg |= divq << HB_PLL_DIVQ_SHIFT;
 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
-- 
1.8.3.2

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