Re: [PATCH] tile: use a more conservative __my_cpu_offset inCONFIG_PREEMPT

From: Will Deacon
Date: Mon Sep 30 2013 - 05:45:26 EST

On Fri, Sep 27, 2013 at 09:13:15PM +0100, Chris Metcalf wrote:
> On 9/26/2013 1:57 PM, Will Deacon wrote:
> > Hi Chris,
> >
> > On Thu, Sep 26, 2013 at 06:24:53PM +0100, Chris Metcalf wrote:
> >> [...]
> >> +static inline unsigned long __my_cpu_offset(void)
> >> +{
> >> + unsigned long tp;
> >> + register unsigned long *sp asm("sp");
> >> + asm("move %0, tp" : "=r" (tp) : "m" (*sp));
> >> + return tp;
> >> +}
> > Hehe, nice to see this hack working out for you too. One thing to check is
> > whether you have any funky addressing modes (things like writeback or
> > post-increment), since the "m" constraint can bite you if you don't actually
> > use it in the asm.
> Well, we do have post increments, though I don't see why this is a problem here.
> We define a target specific constraint "U" that excludes post-increments, but
> again I don't see why "m" would cause trouble here. What was your experience?

GCC assumes that each "m" operand is used *exactly once* in the asm, so if
it decided to generate a post-increment/writeback addressing mode, you can
end up with pointers off by a word if you didn't make use of the constraint
in the code. You can try using "o", but GCC sometimes decides that's
impossible during reload, so we end up combining it with the (undocumented,
ARM-specific) "Q" constraint which is simply a [rN] addressing mode.

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