Re: [PATCH V3] pci: exynos: split into two parts such as Synopsyspart and Exynos part

[Pratyush Anand]

On Thu, Sep 12, 2013 at 06:07:23PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 12 September 2013 03:22 PM, Pratyush Anand wrote:
> > Hi Kishon,
> > 
> > On Thu, Sep 12, 2013 at 05:43:40PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 12 September 2013 03:00 PM, Pratyush Anand wrote:
> >>> Hi Jingoo,
> >>>
> >>>
> >>> On Thu, Sep 12, 2013 at 03:15:04PM +0800, Jingoo Han wrote:
> >>>> On Tuesday 23 July 2013 12:30 PM, Kishon Vijay Abraham I wrote:
> >>>>>>> .
> >>>>>>> .

[...]

> >> when I do ifconfig eth0 up, I get *r8169 0000:01:00.0 eth0: link up.*
> >> But I dont receive any packets and ping also fails and the tx and rx packet
> >> count is also 0. Could it be related to inbound translation?
> > 
> > A PCIe analyser log would tell a definite cause. Most likely either
> > inbound translation is not working or INTx/MSI is not working.
> 
> I have enabled only legacy interrupts. Whenever I connect or disconnect
> ethernet cable I get link up/link down message and also the interrupt count for
> eth0 increases. So I'm not doubting INTx interrupts as such.
> 
> btw configuring inbound translation once in dw_pcie_host_init enough is it? I
> mean we use the same registers for configuring outbound translation also no? So
> doesn't the inbound configuration gets lost?

No, you write at the same register, but you program direction as
inbound. There are different resources for each viewport in inbound
and outbound direction.

Regards
Pratyush

> 
> Thanks
> Kishon
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