Re: [PATCH V3] pci: exynos: split into two parts such as Synopsyspart and Exynos part

[Kishon Vijay Abraham I]

Hi Jingoo,

On Tuesday 23 July 2013 12:30 PM, Jingoo Han wrote:
> On Tuesday, July 23, 2013 3:30 PM, Kishon Vijay Abraham I wrote:
>> On Tuesday 23 July 2013 06:44 AM, Jingoo Han wrote:
>>> On Tuesday, July 23, 2013 12:04 AM, Kishon Vijay Abraham I wrote:
>>>> On Thursday 18 July 2013 10:51 AM, Jingoo Han wrote:
>>>>> Exynos PCIe IP consists of Synopsys specific part and Exynos
>>>>> specific part. Only core block is a Synopsys designware part;
>>>>> other parts are Exynos specific.
>>>>> Also, the Synopsys designware part can be shared with other
>>>>> platforms; thus, it can be split two parts such as Synopsys
>>>>> designware part and Exynos specific part.
>>>>
>>>> some more queries and comments..
>>>
>> .
>> .
>> <snip>
>> .
>> .
>>>>> +			of_pci_range_to_resource(&range, np, &pp->cfg);
>>>>> +			pp->config.cfg0_size = resource_size(&pp->cfg)/2;
>>>>> +			pp->config.cfg1_size = resource_size(&pp->cfg)/2;
>>>>> +		}
>>>>> +	}
>>>>> +
>>>>> +	pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
>>>>> +				resource_size(&pp->cfg));
>>>>
>>>> Why is configuraion space divided into two?
>>>
>>> Sorry, I don't know the exact reason. :(
>>> Pratyush Anand may know about this.
>>> Pratyush Anand, could you answer the question?
>>>
>>> Also, if you find some problems, please let me know.

One more query..

Where is inbound translation configuration done in your driver? how should it
be done?

Thanks
Kishon
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