Re: [PATCH 3/3 V4] EDAC, AMD64_EDAC: Add ECC decoding support for newer F15h models.

From: Aravind Gopalakrishnan
Date: Sat Aug 10 2013 - 14:29:35 EST

On Aug 10, 2013, at 10:15 AM, Borislav Petkov <bp@xxxxxxxxx>

> On Fri, Aug 09, 2013 at 11:54:49AM -0500, Aravind Gopalakrishnan wrote:
>> Adding support for handling ECC error decoding for new F15 models.
>> On newer models, support has been included for upto 4 DCT's, however,
>> only DCT0 and DCT3 are currently configured. (Refer BKDG Section 2.10)
>> Routing DRAM Requests algorithm is different for F15h M30h.
>> It is cleaner to use a brand new function rather than
>> adding quirks in the more generic 'f1x_match_to_this_node'
>> Refer "2.10.5 DRAM Routing Requests" in BKDG for info.
>> Tested on Fam15h M30h with ECC turned on using mce_amd_inj facility and
>> verified to be functionally correct.
>> Changes from V3:
>> - Remove compiler warnings
>> - Recheck models that need erratum workaround for E505:
>> - From looking up history of the bug, we find that
>> the workaround holds true only for Fam15 models upto 1h
>> and only upto stepping 0h. CPU revisions after these
>> do not need the workaround.
>> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@xxxxxxx>
> Ok, I've taken it and applied a cleanup ontop which uses the locally
> cached family, model, stepping (sending it as a reply to this message).
> I'd appreciate it if you tested the branch here
> git:// amd-f15-m30
> just to make sure everything is still kosher.

I have tested the branch and it works fine.


> Thanks.
> --
> Regards/Gruss,
> Boris.
> Sent from a fat crate under my desk. Formatting is fine.
> --

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