Re: [PATCH] perf, x86: Add Silvermont (22nm Atom) support

[Yan, Zheng]

On 07/18/2013 04:27 PM, Yan, Zheng wrote:
> On 07/18/2013 04:23 PM, Peter Zijlstra wrote:
>> On Thu, Jul 18, 2013 at 01:36:07PM +0800, Yan, Zheng wrote:
>>> +static struct event_constraint intel_slm_event_constraints[] __read_mostly =
>>> +{
>>> +	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
>>> +	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
>>> +	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF */
>>> +	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
>>
>> So the normal event 0x13c and the fixed counter 2 are normally _not_ the
>> same. Are they for slm? Are you sure?
>>
> 
> yes, I'm sure. see page 15-15 of http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
> 

I'm sorry, I was wrong.

---
perf stat -e ref-cycles -e cpu/config=0x013c/ sleep 1

 Performance counter stats for 'sleep 1':

         1,181,220 ref-cycles                                                  
            98,434 cpu/config=0x013c/                                          

       0.196653863 seconds time elapsed



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