[PATCH v8 00/14] Tegra114 clockframework

From: Peter De Schrijver
Date: Fri Mar 22 2013 - 08:41:42 EST

This is the eight version of the Tegra114 clockframework. It is based on the
next-20130320-fixed branch of
http://patchwork.ozlabs.org/patch/229972/ and

It has been boottested on Dalmore and Beaverboard.

Changes from v7:

* Fixed dummy operations
* Removed some duplicates from the binding document
* Fixed tegra114_clk enum to be in line with the binding document
* Removed __initdata from tegra_periph_clk_list and
* Mark csite clock as CLK_IGNORE_UNUSED
* Fixed mux mask for disp1 and disp2
* Fixed initializations for PLLX, PLLC, PLLC2 and PLCC3
* Converted clk_pll_wait_for_lock() to use a mask instead of a single bit

Changes from v6:

* Remove clock-frequency from DT serial nodes
* Remove useless 'cpu' clock from binding documentation
* Use HW gate control for PLLU divided outputs
* Fix clock ID for 'd_audio' clock
* Add dummy cpu car ops to ease making a bisectable series

Changes from v5:

* Add initialization code for PLLC
* Remove some unnecessary clocks
* Fix bug in PLL locking refactoring
* Add super clocks
* Remove most calls to clk_register_clkdev() for the peripheral clocks

Changes from v4:

* Split the new PLL types patch into smaller patches
* Fix some bugs in the PLL patches

Changes from v3:

* Merge with for-next branch
* Provide empty tegra_cpu_car_ops to make SMP boot not crash

Changes from v2:

* Added missing PLLs
* Added bindings to tegra114.dtsi
* Moved the table patch for clk-mux.c to 'clk: add table lookup to mux'
* Bugfixes

Changes from v1:

* Remove SATA and PCIe clocks. They don't appear in the internal TRM, so I
assume they don't exist.
* Rebase on top of Hiroshi's latest Tegra114 patches
* More generic mux code. This is necessary for the AHUB and DAM clocks.

Peter De Schrijver (14):
clk: tegra: provide dummy cpu car ops
clk: tegra: Refactor PLL programming code
clk: tegra: Add TEGRA_PLL_BYPASS flag
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
clk: tegra: Add PLL post divider table
clk: tegra: move from a lock bit idx to a lock mask
clk: tegra: Add new fields and PLL types for Tegra114
clk: tegra: Add flags to tegra_clk_periph()
clk: tegra: Workaround for Tegra114 MSENC problem
ARM: tegra: Define Tegra114 CAR binding
clk: tegra: Implement clocks for Tegra114
clk: tegra: devicetree match for nvidia,tegra114-car
ARM: dt: Add references to tegra_car clocks
clk: tegra: Remove forced clk_enable of uartd

.../bindings/clock/nvidia,tegra114-car.txt | 317 +++
arch/arm/boot/dts/tegra114-dalmore.dts | 1 -
arch/arm/boot/dts/tegra114-pluto.dts | 1 -
arch/arm/boot/dts/tegra114.dtsi | 8 +-
drivers/clk/tegra/Makefile | 1 +
drivers/clk/tegra/clk-periph-gate.c | 9 +
drivers/clk/tegra/clk-periph.c | 11 +-
drivers/clk/tegra/clk-pll.c | 1194 ++++++++++--
drivers/clk/tegra/clk-tegra114.c | 2068 ++++++++++++++++++++
drivers/clk/tegra/clk-tegra20.c | 173 +-
drivers/clk/tegra/clk-tegra30.c | 265 ++--
drivers/clk/tegra/clk.c | 4 +-
drivers/clk/tegra/clk.h | 96 +-
13 files changed, 3789 insertions(+), 359 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
create mode 100644 drivers/clk/tegra/clk-tegra114.c


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