Re: [PATCH v2] ioat: remove chanerr mask setting for IOAT v3.x

[Dave Jiang]

On 03/20/2013 10:03 PM, Vinod Koul wrote:
> On Wed, Nov 28, 2012 at 03:46:08AM +0530, Jiang, Dave wrote:
> > The existing code set a value in the PCI_CHANERRMSK_INT register
> > for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that
> > has been fixed when the hardware was released. There is no need for this
> > code.
> >
> > Signed-off-by: Dave Jiang <dave.jiang@xxxxxxxxx>
> > ---
> >
> >   drivers/dma/ioat/dma_v3.c |    7 +------
> >   1 file changed, 1 insertion(+), 6 deletions(-)
> >
> > diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
> > index f7f1dc6..fda3b8a1 100644
> > --- a/drivers/dma/ioat/dma_v3.c
> > +++ b/drivers/dma/ioat/dma_v3.c
> > @@ -1126,12 +1126,7 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan)
> >   	chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
> >   	writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
> >   
> > -	/* -= IOAT ver.3 workarounds =- */
> > -	/* Write CHANERRMSK_INT with 3E07h to mask out the errors
> > -	 * that can cause stability issues for IOAT ver.3, and clear any
> > -	 * pending errors
> > -	 */
> What is this code based against? i dont have above lines in -rc1 or my next?
Looking at the Linus tree it looks like it's already upstream somehow? 
Commit 6decffd.

> > -	pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
> > +	/* clear any pending errors */
> >   	err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
> >   	if (err) {
> >   		dev_err(&pdev->dev, "channel error register unreachable\n");

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