[PATCHv2 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

From: Stephen Boyd
Date: Mon Mar 18 2013 - 14:29:50 EST

From: Stepan Moskovchenko <stepanm@xxxxxxxxxxxxxx>

Some early versions of the Krait CPU design incorrectly indicate
that they only support the UDIV and SDIV instructions in Thumb
mode when they actually support them in ARM and Thumb mode. It
seems that these CPUs follow the DDI0406B ARM ARM which has two
possible values for the divide instructions field, instead of the
DDI0406C document which has three possible values.

Work around this problem by checking the MIDR against Krait CPUs
with this faulty ISAR0 register and force the hwcaps to indicate
support in both modes.

Cc: Will Deacon <will.deacon@xxxxxxx>
Signed-off-by: Stepan Moskovchenko <stepanm@xxxxxxxxxxxxxx>
[sboyd: Rewrote commit text to reflect real reasoning now that
we autodetect udiv/sdiv]
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
arch/arm/mm/proc-v7.S | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index bcd3d48..f584d3f 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -434,6 +434,21 @@ __v7_ca15mp_proc_info:
.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info

+ * Qualcomm Inc. Krait processors.
+ */
+ .type __krait_proc_info, #object
+ .long 0x510f0400 @ Required ID value
+ .long 0xff0ffc00 @ Mask for ID
+ /*
+ * Some Krait processors don't indicate support for SDIV and UDIV
+ * instructions in the ARM instruction set, even though they actually
+ * do support them.
+ */
+ __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
+ .size __krait_proc_info, . - __krait_proc_info
+ /*
* Match any ARMv7 processor core.
.type __v7_proc_info, #object
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