Re: [PATCH 4/5] perf, x86: Support full width counting v3

[Ingo Molnar]

* Andi Kleen <andi@xxxxxxxxxxxxxx> wrote:

> Recent Intel CPUs like Haswell and IvyBridge have a new 
> alternative MSR range for perfctrs that allows writing the 
> full counter width. Enable this range if the hardware reports 
> it using a new capability bit.
> 
> This lowers the overhead of perf stat slightly because it has
> to do less interrupts to accumulate the counter value. On
> Haswell it also avoids some problems with TSX aborting when
> the end of the counter range is reached.
>
> This can be observed when the checkpoint flag has been set, 
> which has been enabled by the basic PMU patch. An overflow 
> will abort the transaction and set the counter back. If the 
> counter is near the overflow before the transaction this could 
> happen continuously, forcing a transaction to continuously 
> abort.
>
> This is a partial fix, but it makes the overflows much less 
> likely by using a larger counter, to lower the probability of 
> the event. Additional counter measures are in the additional 
> extended Haswell patchkit.

It would actually be _much_ more useful to first try to fix that 
condition - then extend the counter range. As you say it in the 
changelog it can happen anyway: and it's much more testable if 
the counter width is narrower initially.

Mind restructuring the basic patches thusly, putting the fix 
first and moving the counter extension to the later patches?

(If you don't have the time for that we can delay it all to 
v3.10, it's pretty late already even for v3.9.)

Thanks,

	Ingo
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