Re: [PATCH] clk: tegra: initialise parent of uart clocks

[Peter De Schrijver]

On Wed, Feb 06, 2013 at 11:47:41AM +0100, Laxman Dewangan wrote:
> Initialise the parent of UARTs to PLLP and disabling clock by
> default.
> 

I wonder if we should move the parent definitions to DT at some point.

Cheers,

Peter.
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