[tip:perf/x86] perf/x86: Export PEBS load latency threshold register to sysfs

[tip-bot for Stephane Eranian]

Commit-ID:  5a54b18a9e9c77ebd1d30d4544e4f936fcafa6b9
Gitweb:     http://git.kernel.org/tip/5a54b18a9e9c77ebd1d30d4544e4f936fcafa6b9
Author:     Stephane Eranian <eranian@xxxxxxxxxx>
AuthorDate: Thu, 24 Jan 2013 16:10:33 +0100
Committer:  Ingo Molnar <mingo@xxxxxxxxxx>
CommitDate: Fri, 25 Jan 2013 10:19:04 +0100

perf/x86: Export PEBS load latency threshold register to sysfs

Make the PEBS Load Latency threshold register layout
and encoding visible to user level tools.

Signed-off-by: Stephane Eranian <eranian@xxxxxxxxxx>
Cc: peterz@xxxxxxxxxxxxx
Cc: ak@xxxxxxxxxxxxxxx
Cc: acme@xxxxxxxxxx
Cc: jolsa@xxxxxxxxxx
Cc: namhyung.kim@xxxxxxx
Link: http://lkml.kernel.org/r/1359040242-8269-10-git-send-email-eranian@xxxxxxxxxx
Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
---
 arch/x86/kernel/cpu/perf_event_intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index f30027a..4ee1211 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1756,6 +1756,8 @@ static void intel_pmu_flush_branch_stack(void)
 
 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
 
+PMU_FORMAT_ATTR(ldlat, "config1:0-15");
+
 static struct attribute *intel_arch3_formats_attr[] = {
 	&format_attr_event.attr,
 	&format_attr_umask.attr,
@@ -1766,6 +1768,7 @@ static struct attribute *intel_arch3_formats_attr[] = {
 	&format_attr_cmask.attr,
 
 	&format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
+	&format_attr_ldlat.attr, /* PEBS load latency */
 	NULL,
 };
 
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