Re: [PATCH 1/1] perf, Add support for Xeon-Phi PMU

[Cyrill Gorcunov]

On Tue, Sep 25, 2012 at 03:42:25PM +0400, Cyrill Gorcunov wrote:
> On Tue, Sep 25, 2012 at 01:32:38PM +0200, Peter Zijlstra wrote:
> > On Thu, 2012-09-20 at 13:03 -0400, Vince Weaver wrote:
> > > One additional complication:  some of the cache events map to 
> > > event "0".  This causes problems because the generic events code
> > > assumes "0" means not-available.  I'm not sure the best way to address
> > > that problem. 
> > 
> > For all except P4 we could remap the 0 value to -2, that has all high
> > bits set (like the -1) which aren't used by hardware.
> > 
> > P4 is stuffing two registers in the 64bit config space and actually has
> > them all in use I think.. Cyrill?
> 
> Yeah, we use almost all 64 bits in config. I tried to describe the bitmaps
> in perf_event_p4.h (see Notes on internal configuration of ESCR+CCCR tuples).
> 
> Guys, letme re-read this whole mail thread first since I have no clue
> what this remapping about ;)

If we need some special mark in config I can try to free hight bit in
@config and move it somehwere in low 32 bits (there are bits 28-29 which
i can use for that). Ie I can provide the sign bit, would it be enough?
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