Re: [PATCH] Add 2-level GPUVM pagetables support to radeon driver.

From: Christian König
Date: Fri Sep 14 2012 - 04:49:35 EST

On 13.09.2012 20:42, Jerome Glisse wrote:
On Thu, Sep 13, 2012 at 2:37 PM, Alex Deucher <alexdeucher@xxxxxxxxx> wrote:
On Thu, Sep 13, 2012 at 2:17 PM, Jerome Glisse <j.glisse@xxxxxxxxx> wrote:
On Thu, Sep 13, 2012 at 10:13 AM, Dmitry Cherkasov
<dcherkassov@xxxxxxxxx> wrote:
PDE/PTE update code uses CP ring for memory writes.
All page table entries are preallocated for now in alloc_pt().

It is made as whole because it's hard to divide it to several patches
that compile and doesn't break anything being applied separately.

Tested on cayman card.

Signed-off-by: Dmitry Cherkasov <Dmitrii.Cherkasov@xxxxxxx>
I couldn't test in on SI card, so would be happy if someone could check it there.
I wonder how this could have work as you don't set
PAGE_TABLE_BLOCK_SIZE field so each page directory entry cover only 1
I think PAGE_TABLE_BLOCK_SIZE refers number of 4k pages used for PTE
entries per PDE. E.g., 1 4k page contains 512 64 bit PTEs. so if
BLOCK_SIZE is set to 1 page, each PDE points to 1 page (4k) or PTE
entries. If BLOCK_SIZE is 2, each PDE points to 2 pages (8k) or PTEs,


If so then it's ok
Yeah, minor nitpick: BLOCK_SIZE seems to be number of 4k pages in a page directory entry minus 1.

So with a BLOCK_SIZE of 0 you get one 4K page and with a BLOCK_SIZE of 1 you get 8K, etc...

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