Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value forSRC/DST_TR_WID register

[Andy Shevchenko]

On Mon, Sep 3, 2012 at 11:30 AM, Viresh Kumar <viresh.kumar@xxxxxxxxxx> wrote:
> On 3 September 2012 13:55, Andy Shevchenko <andy.shevchenko@xxxxxxxxx> wrote:
>>> #define DW_MEM_WIDTH_64         0       /* default */
>>> #define DW_MEM_WIDTH_32         1       /* e.g. for avr32 */
>> There are 4 options: 32, 64, 128, and 256 bits. I would prefer to see
>> the value in conjunction with
>> real value in the register, namely 2 for 32, 3 - 64, 4 - 128, 5 - 256.
>
> Which register are you talking about? This configuration is outside of DMAC
> controller and i am not sure if dw DMAC controller can do 128 or 256
> bit transfers.
SRC_WIDTH & DST_WIDTH in CTLx. The field are 3 bit long. Acceptable
values from 0 to 5.
2 corresponds to 32 bit transfers.

>>> @@ -58,6 +58,9 @@ struct dw_dma_slave {
>>>         u32                     cfg_lo;
>>>         u8                      src_master;
>>>         u8                      dst_master;
>>> +#define        DW_MEM_WIDTH_64         0
>>> +#define        DW_MEM_WIDTH_32         1       /* e.g. for avr32 */
>>> +       u8                      max_mem_width;
>> Might be I missed something, but why is it slave configuration?
>> I think the controller (actually channel) structure is more suitable
>> to keep that field inside.
>
> @Hein: Even i missed it. How will you do memcpy transfers as we don't have
> this structure there. Probably you need to move this to DMA controller platform
> data filed.
>
> viresh



-- 
With Best Regards,
Andy Shevchenko
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