[ 056/108] e1000e: Correct link check logic for 82571 serdes

From: Ben Hutchings
Date: Sun Jul 22 2012 - 21:52:59 EST

3.2-stable review patch. If anyone has any objections, please let me know.


From: Tushar Dave <tushar.n.dave@xxxxxxxxx>

commit d0efa8f23a644f7cb7d1f8e78dd9a223efa412a3 upstream.

SYNCH bit and IV bit of RXCW register are sticky. Before examining these bits,
RXCW should be read twice to filter out one-time false events and have correct
values for these bits. Incorrect values of these bits in link check logic can
cause weird link stability issues if auto-negotiation fails.

Reported-by: Dean Nelson <dnelson@xxxxxxxxxx>
Signed-off-by: Tushar Dave <tushar.n.dave@xxxxxxxxx>
Reviewed-by: Bruce Allan <bruce.w.allan@xxxxxxxxx>
Tested-by: Jeff Pieper <jeffrey.e.pieper@xxxxxxxxx>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@xxxxxxxxx>
Signed-off-by: Ben Hutchings <ben@xxxxxxxxxxxxxxx>
drivers/net/ethernet/intel/e1000e/82571.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/intel/e1000e/82571.c b/drivers/net/ethernet/intel/e1000e/82571.c
index 36db4df..1f063dc 100644
--- a/drivers/net/ethernet/intel/e1000e/82571.c
+++ b/drivers/net/ethernet/intel/e1000e/82571.c
@@ -1572,6 +1572,9 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
ctrl = er32(CTRL);
status = er32(STATUS);
rxcw = er32(RXCW);
+ /* SYNCH bit and IV bit are sticky */
+ udelay(10);
+ rxcw = er32(RXCW);

if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {

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