Re: [PATCH 1/2] perf, x86: Add basic Ivy Bridge support

[Stephane Eranian]

Also IVB needs its own pebs_constraint table as there is a new PEBS
event (0xd3):

+struct event_constraint intel_ivb_pebs_event_constraints[] = {
+       INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.ALL */
+       INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
+       INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
+       INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
+       INTEL_EVENT_CONSTRAINT(0xcd, 0x8),    /* MEM_TRANS_RETIRED.* */
+       INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
+       INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
+       INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /*
MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
+       INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /*
MEM_LOAD_UOPS_LLC_MISS.LOCAL_DRAM */
+       EVENT_CONSTRAINT_END
+};
+


On Fri, Jun 8, 2012 at 12:43 AM, Andi Kleen <ak@xxxxxxxxxxxxxxx> wrote:
>> But as far as I know for the other generic stall event:
>> Â Â Â Â Â Â Â Â/* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
>> Â Â Â Â Â Â Â Â intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
>> Â Â Â Â Â Â Â Â Â Â Â Â X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
>
> Okay. ÂI'll just undefine it.
>
> -Andi
>
>
> --
> ak@xxxxxxxxxxxxxxx -- Speaking for myself only
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