Re: perf, x86: only do lbr init if bts is available

[David Ahern]

On 5/24/12 10:41 AM, David Ahern wrote:
> On 5/24/12 10:35 AM, Stephane Eranian wrote:
> > Where is the wrmsr coming from? What we need to do is ensure that LBR
> > is not
> > touched if we don't actually use it.
>
> e.g., intel_pmu_lbr_init_nhm sets up lbr_nr, lbr_from, lbr_to and from,
> etc. Fhat I can tell intel_pmu_lbr_reset() gets invoked some where
> during the VM boot; I haven't traced how/when yet.

[    0.012998]  [<c04220ca>] intel_pmu_lbr_reset+0x2a/0xa0
[    0.012998]  [<c0423beb>] intel_pmu_cpu_starting+0x3b/0x100
[    0.012998]  [<c0424bd0>] ? allocate_shared_regs+0x20/0x50
[    0.012998]  [<c0932714>] x86_pmu_notifier+0xb3/0xc0
[    0.012998]  [<c0bed54c>] init_hw_perf_events+0x42c/0x456
[    0.012998]  [<c0403034>] do_one_initcall+0x34/0x170
[    0.012998]  [<c0bf2388>] ? native_smp_prepare_cpus+0x2b7/0x2f2
[    0.012998]  [<c0bed120>] ? check_bugs+0xf9/0xf9
[    0.012998]  [<c0be4833>] kernel_init+0x77/0x1a4
[    0.012998]  [<c0be47bc>] ? start_kernel+0x36d/0x36d
[    0.012998]  [<c094af7e>] kernel_thread_helper+0x6/0x10

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