Re: [PATCH v7 8/8] x86/tlb: just do tlb flush on one of siblingsof SMT

[Arjan van de Ven]

On 5/24/2012 7:32 AM, Alex Shi wrote:
>>>> we really really shouldn't do flushing of tlb's on only one half of SMT.
> 
>>>> SMT sibblings have their own TLB pool at least on some of Intels chips.
>>>
>>>
>>> That is also the biggest question I want to know. Actually, some
>>> documents, wiki said the SMT sibling just has process registers and
>>> interrupt part, no any tlb/l1 cache etc, (like intel's doc
>>> vol6iss1_hyper_threading_technology.pdf).  And the patch runs well on
>>> NHM EP/WSM EP/NHM EX/SNB EP CPUs.
>>>
>>> But hard to get such clearly per cpu info of SMT/HT, so, what the
>>> detailed Intel chips has 'TLB pool' on SMT?
>>
>> all of them.
>>
>> the TLB pool is shared as physical resource (dynamic or static, that
>> depends), but each tlb entry will be tagged for which of the two HT
>> pairs it's for, and on a logical level, they are completely separate as
>> a result (as they should be)
> 
> 
> But, why just flush part of SMT doesn't crash kernel on many benchmarks
> testing? 

stale tlb's don't crash the kernel
they do random weird **** to userspace processes.

you REALLY don't want to be debugging those.

There is absolutely NO GUARANTEE that a full tlbflush on one thread
flushes the other one. (in fact I'd be surprised if it actually did).

Also remember that there are several levels of TLB and tlb caches, and
you HAVE to flush all.
Intel put out a very clear document about the rules around TLBs
(it's on the same URL as the SDM, if it hasn't been absorbed into the
SDM already)... and we have to follow those rules.
(Linux already followed those rules even prior to that doc existing,
but the rules are at least very explicit now)

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