Re: [PATCH] perf, x86: Optimal way of reading LBR entries insideIntel PMU interrupt handler

[Stephane Eranian]

On Tue, May 22, 2012 at 1:10 PM, Anshuman Khandual
<khandual@xxxxxxxxxxxxxxxxxx> wrote:
> perf, x86: Optimal way of reading LBR entries inside Intel PMU interrupt handler
>
> Â Â Â ÂWe read LBR entries even if no event has requested for it either explicitly
> Â Â Â Âthrough branch sampling or implicitly through precise IP. This patch would
> Â Â Â Âfix this potential unnecessary read by moving the intel_pmu_lbr_read function.
>
But that's not quite the case because intel_pmu_lbr_read() checks:

       if (!cpuc->lbr_users)
                return;

> Signed-off-by: Anshuman Khandual <khandual@xxxxxxxxxxxxxxxxxx>
> ---
> Âarch/x86/kernel/cpu/perf_event_intel.c | Â 12 +++++++++---
> Â1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 26b3e2f..c50da47 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -1026,6 +1026,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
> Â Â Â Âint bit, loops;
> Â Â Â Âu64 status;
> Â Â Â Âint handled;
> + Â Â Â int lbr_read;
>
> Â Â Â Âperf_sample_data_init(&data, 0);
>
> @@ -1061,16 +1062,16 @@ again:
>
> Â Â Â Âinc_irq_stat(apic_perf_irqs);
>
> - Â Â Â intel_pmu_lbr_read();
> -
> Â Â Â Â/*
> Â Â Â Â * PEBS overflow sets bit 62 in the global status register
> Â Â Â Â */
> Â Â Â Âif (__test_and_clear_bit(62, (unsigned long *)&status)) {
> Â Â Â Â Â Â Â Âhandled++;
> + Â Â Â Â Â Â Â intel_pmu_lbr_read();
> Â Â Â Â Â Â Â Âx86_pmu.drain_pebs(regs);
> Â Â Â Â}
>
> + Â Â Â lbr_read = 0;
> Â Â Â Âfor_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
> Â Â Â Â Â Â Â Âstruct perf_event *event = cpuc->events[bit];
>
> @@ -1084,8 +1085,13 @@ again:
>
> Â Â Â Â Â Â Â Âdata.period = event->hw.last_period;
>
> - Â Â Â Â Â Â Â if (has_branch_stack(event))
> + Â Â Â Â Â Â Â if (has_branch_stack(event)) {
> + Â Â Â Â Â Â Â Â Â Â Â if(lbr_read == 0) {
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â intel_pmu_lbr_read();
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â lbr_read = 1;
> + Â Â Â Â Â Â Â Â Â Â Â }
> Â Â Â Â Â Â Â Â Â Â Â Âdata.br_stack = &cpuc->lbr_stack;
> + Â Â Â Â Â Â Â }
>
> Â Â Â Â Â Â Â Âif (perf_event_overflow(event, &data, regs))
> Â Â Â Â Â Â Â Â Â Â Â Âx86_pmu_stop(event, 0);
>
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