Re: [PATCH v5 6/7] x86/tlb: optimizing flush_tlb_mm

[Alex Shi]

On 05/15/2012 09:06 PM, Peter Zijlstra wrote:

> On Tue, 2012-05-15 at 20:58 +0800, Luming Yu wrote:
>>
>>
>> Both __native_flush_tlb() and __native_flush_tlb_single(...)
>> introduced roughly 1 ns  latency to tsc sampling executed in
>> stop_machine_context in two logical CPUs 
> 
> But you have to weight that against the cost of re-population, and
> that's the difficult bit, since we have no clue how many tlb entries are
> in use by the current cr3.
> 
> It might be possible for intel to give us this information, I've asked
> for something similar for cachelines.
> 


I don't know if such info exist in cpu. Maybe US engineer know more.
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