RE: [PATCH 2/2] x86/mce: Add instruction recovery signatures tomce-severity table

[Luck, Tony]

> For IFU, on affected logical processors, RIPV and EIPV both are 0,
> since now new IFU entries are added into severity table, the old
> entry as below should be removed:
>
> /* Neither return not error IP -- no chance to recover -> PANIC */
>        MCESEV(
>                PANIC, "Neither restart nor error IP",
>                MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
>                ),

We need to keep this. If EIPV is not set, then CS and IP on the
stack are not guaranteed ... so we can't tell whether the error
happened in user or kernel mode. This makes recovery "challenging".

I'm trying to figure out a quirk for processors that do generate
EIPV=RIPV=0 signature for IFU errors. There are some case where
we can work around the lack of EIPV.

-Tony

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