Re: [RFC 00/15] perf: Add backtrace post dwarf unwind

[Peter Zijlstra]

On Thu, 2012-03-29 at 17:38 -0700, Stephane Eranian wrote:
> What I'd like to have is something similar to:
>     attr->sample_type |= PERF_SAMPLE_REGS
>     attr->sample_regs = EAX | EBX | EDI | ESI |.....
>     attr->sample_reg_mode = { INTR, PRECISE, USER }
> 
> Then in each sample for the event you dump the u64 values
> of the requested registers.  The order is that of the enum
> enum regs {}. That enum is arch specific.
> 
> When you are in precise mode on Intel, you extract the regs
> from PEBS. You already know the registers supported by PEBS
> so you can reject any request for  unsupported regs.
> 
> When you are in intr they you get the regs from pt_regs.
> The user mode case is taken care of by the this patch series
> already.
> 
> I am not sure the sample_reg_mode needs to be a bitmask, i.e.,
> do we need the reg state for INTR+PRECISE or USER+INTR?
> But if so, then we would need attr->sample_regs[3] as not all
> registers may be available in each mode. 

I'm really having trouble seeing how useful this is. You mentioned
sampling function arguments, but most samples would be in the middle of
functions where the regs are completely unrelated to arguments. Also
isn't the 'normal' C ABI passing args on stack rather than registers?



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