0001-i.MX35-PDK-Chunghwa-CLAA070VC01-7-WVGA-TFT-Display-s.patch

From: Alex Gershgorin
Date: Mon Mar 05 2012 - 12:05:28 EST


From 63124d8b4bbcfea877f0ed736238c53f940f325f Mon Sep 17 00:00:00 2001
From: Alex <alexg@xxxxxxxxxxxxxx>
Date: Mon, 5 Mar 2012 14:19:08 +0200
Subject: [PATCH] i.MX35 PDK: Chunghwa CLAA070VC01 7" WVGA TFT Display support

This patch add support for display that shipped with the i.MX35 PDK.

Signed-off-by: Alex Gershgorin <alexg@xxxxxxxxxxxxxx>
---
arch/arm/mach-imx/mach-mx35_3ds.c | 57 +++++++++++++++++++++++++++++++++++++
1 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c..a477e46 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -120,6 +120,61 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
/* I2C1 */
MX35_PAD_I2C1_CLK__I2C1_SCL,
MX35_PAD_I2C1_DAT__I2C1_SDA,
+ /* DISPLAY */
+ MX35_PAD_LD0__IPU_DISPB_DAT_0,
+ MX35_PAD_LD1__IPU_DISPB_DAT_1,
+ MX35_PAD_LD2__IPU_DISPB_DAT_2,
+ MX35_PAD_LD3__IPU_DISPB_DAT_3,
+ MX35_PAD_LD4__IPU_DISPB_DAT_4,
+ MX35_PAD_LD5__IPU_DISPB_DAT_5,
+ MX35_PAD_LD6__IPU_DISPB_DAT_6,
+ MX35_PAD_LD7__IPU_DISPB_DAT_7,
+ MX35_PAD_LD8__IPU_DISPB_DAT_8,
+ MX35_PAD_LD9__IPU_DISPB_DAT_9,
+ MX35_PAD_LD10__IPU_DISPB_DAT_10,
+ MX35_PAD_LD11__IPU_DISPB_DAT_11,
+ MX35_PAD_LD12__IPU_DISPB_DAT_12,
+ MX35_PAD_LD13__IPU_DISPB_DAT_13,
+ MX35_PAD_LD14__IPU_DISPB_DAT_14,
+ MX35_PAD_LD15__IPU_DISPB_DAT_15,
+ MX35_PAD_LD16__IPU_DISPB_DAT_16,
+ MX35_PAD_LD17__IPU_DISPB_DAT_17,
+ MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+ MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+ MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+ MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+ MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
+};
+
+static const struct fb_videomode fb_modedb[] = {
+ {
+ /* 800x480 @ 60 Hz */
+ .name = "CTP-CLAA070LC0ACW",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(27000),
+ .left_margin = 50,
+ .right_margin = 50, /* whole line should have 900 clocks */
+ .upper_margin = 10,
+ .lower_margin = 10, /* whole frame should have 500 lines */
+ .hsync_len = 1, /* note: DE only display */
+ .vsync_len = 1, /* note: DE only display */
+ .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+};
+
+static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+ .name = "CTP-CLAA070LC0ACW",
+ .mode = fb_modedb,
+ .num_modes = ARRAY_SIZE(fb_modedb),
};

static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -204,6 +259,8 @@ static void __init mx35_3ds_init(void)
pr_warn("Init of the debugboard failed, all "
"devices on the debugboard are unusable.\n");
imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+ imx35_add_ipu_core(&mx35_3ds_ipu_data);
+ imx35_add_mx3_sdc_fb(&mx3fb_pdata);
}

static void __init mx35pdk_timer_init(void)
--
1.7.0.4