Re: [PATCH] Clear previous interrupts after fifo is disabled

[Chanho Min]

> Because the flags are manipulated to give the illusion of a one byte
> FIFO, as stated in the TRM.
Yes. It is the problem that rx interrupt is pended with this status as
I mentioned.

> And we don't set the mask register to 1 until later.
In the last part of startup, set to 1. Interrupt can be occurred just after it.

uap->im = UART011_RTIM;
if (!pl011_dma_rx_running(uap))
 uap->im |= UART011_RXIM;
 writew(uap->im, uap->port.membase + UART011_IMSC);

> But we want to do the transmit interrupt provocation with the FIFO disabled.
I know. It's test only.
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