Re: RAS trace event proto

[Borislav Petkov]

On Wed, Feb 22, 2012 at 10:02:16AM -0200, Mauro Carvalho Chehab wrote:
> Using the same concept I've adopted for my EDAC patches, I would map the 
> above into 3 fields:
> 
> 	CPU instance = 64
> 	error message = Instruction Cache Error: L1 TLB multimatch.
> 	detail = cache level: L1, tx: INSN
> 	(or, maybe, detail = [-|CE|MiscV|PCC|-|CECC] cache level: L1, tx: INSN)

No, this is not going to fly the moment you decide to dump MCi_ADDR
because it is relevant for a certain types of errors:

[ 1121.970020] [Hardware Error]: CPU:64   MC2_STATUS[Over|CE|-|-|AddrV|CECC]: 0xd400400000000813
[ 1121.979039] [Hardware Error]:  MC2_ADDR: 0xbabedeaddeadbeef
[ 1121.979042] [Hardware Error]: Bus Unit Error: RD/ECC error in data read from NB.
[ 1121.979047] [Hardware Error]: cache level: L3/GEN, mem/io: MEM, mem-tx: RD, part-proc: SRC (no timeout)

The whole decoded thing above is a string and the MCA registers are
passed on into the trace, _in_ _addition_.

IOW, for each tracepoint, the format should be a string which is
possibly empty and describes the error message additionally, and the
remaining register attributes, one per field. Mapping the hw error
scheme to some memory error format you've come up with is a bad idea and
a no-no.

-- 
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Boris.

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