[24/65] ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards

From: Greg KH
Date: Wed Feb 01 2012 - 16:08:27 EST

3.0-stable review patch. If anyone has any objections, please let me know.


From: Will Deacon <will.deacon@xxxxxxx>

commit 612539e81f655f6ac73c7af1da8701c1ee618aee upstream.

On v7, we use the same cache maintenance instructions for data lines
as for unified lines. This was not the case for v6, where HARVARD_CACHE
was defined to indicate the L1 cache topology.

This patch removes the erroneous compile-time check for HARVARD_CACHE in
proc-v7.S, ensuring that we perform I-side invalidation at boot.

Reported-and-Acked-by: Shawn Guo <shawn.guo@xxxxxxxxxx>

Acked-by: Catalin Marinas <Catalin.Marinas@xxxxxxx>
Signed-off-by: Will Deacon <will.deacon@xxxxxxx>
Signed-off-by: Russell King <rmk+kernel@xxxxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>

arch/arm/mm/proc-v7.S | 6 ------
1 file changed, 6 deletions(-)

--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -270,10 +270,6 @@ cpu_resume_l1_flags:
* Initialise TLB, Caches, and MMU state ready to switch the MMU
* on. Return in r0 the new CP15 C1 control register setting.
- * We automatically detect if we have a Harvard cache, and use the
- * Harvard cache control instructions insead of the unified cache
- * control instructions.
- *
* This should be able to cover all ARMv7 cores.
* It is assumed that:
@@ -363,9 +359,7 @@ __v7_setup:

3: mov r10, #0
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs

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