Re: [PATCH v1 8/8] ARM: tegra: support for secondary cores on Tegra30

[Murali N]

On Thu, Jan 26, 2012 at 10:37 PM, Peter De Schrijver
<pdeschrijver@xxxxxxxxxx> wrote:
>
> Add support for bringing up secondary cores on Tegra30. On Tegra30 secondary
> CPU cores are powergated, so we need to turn on the domains before we can bring
> the CPU cores online. Bringing secondary cores online happens early during the
> ssytem boot, so we call powergating initialization from platform early_init

small spelling correction "system"

> function.
>
> Based on work by:
>
> Scott Williams <scwilliams@xxxxxxxxxx>
> Colin Cross <ccross@xxxxxxxxxxx>
> Alex Frid <afrid@xxxxxxxxxx>
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
> ---
> Âarch/arm/mach-tegra/headsmp.S | Â 32 +++++++++++++++++++++++++
> Âarch/arm/mach-tegra/platsmp.c | Â 52 ++++++++++++++++++++++++++++++++++++++++-
> Â2 files changed, 83 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
> index bb13e22..925c4a0 100644
> --- a/arch/arm/mach-tegra/headsmp.S
> +++ b/arch/arm/mach-tegra/headsmp.S
> @@ -188,6 +188,38 @@ __die:
>    Âstr   r1, [r7, #0x340]        Â@ CLK_RST_CPU_CMPLX_SET
> Â#endif
> Â1:
> +#ifdef CONFIG_ARCH_TEGRA_3x_SOC
> + Â Â Â mov32 Â r6, TEGRA_FLOW_CTRL_BASE
> +
> +    cmp   r10, #0
> +    moveq  r1, #FLOW_CTRL_HALT_CPU0_EVENTS
> +    moveq  r2, #FLOW_CTRL_CPU0_CSR
> +    movne  r1, r10, lsl #3
> +    addne  r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
> +    addne  r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
> +
> + Â Â Â /* Clear CPU "event" and "interrupt" flags and power gate
> + Â Â Â Â Âit when halting but not before it is in the "WFI" state. */
> +    ldr   r0, [r6, +r2]
> +    orr   r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
> +    orr   r0, r0, #FLOW_CTRL_CSR_ENABLE
> +    str   r0, [r6, +r2]
> +
> + Â Â Â /* Unconditionally halt this CPU */
> +    mov   r0, #FLOW_CTRL_WAITEVENT
> +    str   r0, [r6, +r1]
> +    ldr   r0, [r6, +r1]          @ memory barrier
> +
> + Â Â Â dsb
> + Â Â Â isb
> +    wfi                   @ CPU should be power gated here
> +
> + Â Â Â /* If the CPU didn't power gate above just kill it's clock. */
> +
> +    mov   r0, r11, lsl #8
> +    str   r0, [r7, #348]         Â@ CLK_CPU_CMPLX_SET
> +#endif
> +
> Â Â Â Â/* If the CPU still isn't dead, just spin here. */
>    Âb    .
> ÂENDPROC(__tegra_cpu_reset_handler)
> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> index fa1178d..672a751 100644
> --- a/arch/arm/mach-tegra/platsmp.c
> +++ b/arch/arm/mach-tegra/platsmp.c
> @@ -24,7 +24,9 @@
> Â#include <asm/mach-types.h>
> Â#include <asm/smp_scu.h>
>
> +#include <mach/clk.h>
> Â#include <mach/iomap.h>
> +#include <mach/powergate.h>
>
> Â#include "chipid.h"
> Â#include "flowctrl.h"
> @@ -42,6 +44,8 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
> Â Â Â Â(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
> Â#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
> Â Â Â Â(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
> +#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
> + Â Â Â (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
>
> Â#define CPU_CLOCK(cpu) (0x1<<(8+cpu))
> Â#define CPU_RESET(cpu) (0x1111ul<<(cpu))
> @@ -73,11 +77,54 @@ static int tegra20_power_up_cpu(unsigned int cpu)
> Â Â Â Âreturn 0;
> Â}
>
> +static int tegra30_power_up_cpu(unsigned int cpu)
> +{
> + Â Â Â u32 reg;
> + Â Â Â int ret, pwrgateid;
> + Â Â Â unsigned long timeout;
> +
> + Â Â Â pwrgateid = tegra_cpu_powergate_id(cpu);
> + Â Â Â if (pwrgateid < 0)
> + Â Â Â Â Â Â Â return pwrgateid;
> +
> + Â Â Â /* If this is the first boot, toggle powergates directly. */
> + Â Â Â if (!tegra_powergate_is_powered(pwrgateid)) {
> + Â Â Â Â Â Â Â ret = tegra_powergate_power_on(pwrgateid);
> + Â Â Â Â Â Â Â if (ret)
> + Â Â Â Â Â Â Â Â Â Â Â return ret;
> +
> + Â Â Â Â Â Â Â /* Wait for the power to come up. */
> + Â Â Â Â Â Â Â timeout = jiffies + 10*HZ;
> + Â Â Â Â Â Â Â do {
> + Â Â Â Â Â Â Â Â Â Â Â if (tegra_powergate_is_powered(pwrgateid))
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â goto remove_clamps;
> + Â Â Â Â Â Â Â Â Â Â Â udelay(10);
> + Â Â Â Â Â Â Â } while (time_before(jiffies, timeout));
> + Â Â Â Â Â Â Â return -ETIMEDOUT;
> + Â Â Â }
> +
> +remove_clamps:
> + Â Â Â /* CPU partition is powered. Enable the CPU clock. */
> + Â Â Â writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
> + Â Â Â reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
> + Â Â Â udelay(10);
> +
> + Â Â Â /* Remove I/O clamps. */
> + Â Â Â ret = tegra_powergate_remove_clamping(pwrgateid);
> + Â Â Â udelay(10);
> +
> + Â Â Â /* Clear flow controller CSR. */
> + Â Â Â flowctrl_write_cpu_csr(cpu, 0);
> +
> + Â Â Â return 0;
> +}
> +
> Âint __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> Â{
> Â Â Â Âint status;
>
> - Â Â Â /* Force the CPU into reset. The CPU must remain in reset when the
> + Â Â Â /*
> + Â Â Â Â* Force the CPU into reset. The CPU must remain in reset when the
> Â Â Â Â * flow controller state is cleared (which will cause the flow
> Â Â Â Â * controller to stop driving reset if the CPU has been power-gated
> Â Â Â Â * via the flow controller). This will have no effect on first boot
> @@ -98,6 +145,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> Â Â Â Âcase TEGRA20:
> Â Â Â Â Â Â Â Âstatus = tegra20_power_up_cpu(cpu);
> Â Â Â Â Â Â Â Âbreak;
> + Â Â Â case TEGRA30:
> + Â Â Â Â Â Â Â status = tegra30_power_up_cpu(cpu);
> + Â Â Â Â Â Â Â break;
> Â Â Â Âdefault:
> Â Â Â Â Â Â Â Âstatus = -EINVAL;
> Â Â Â Â Â Â Â Âbreak;
> --
> 1.7.7.rc0.72.g4b5ea.dirty
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




--
Regards,
Murali N
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