linux-next: manual merge of the driver-core tree with the arm tree

[Stephen Rothwell]

Hi Greg,

Today's linux-next merge of the driver-core tree got a conflict in
arch/arm/mach-s3c64xx/common.c between commit b024043b6d0d ("ARM: 7245/1:
S3C64XX: introduce arch/arm/mach-s3c64xx/common.[ch]") from the arm tree
and commit edbaa603eb80 ("driver-core: remove sysdev.h usage") from the
driver-core tree (where it is called arch/arm/mach-s3c64xx/irq-eint.c).

Just context changes.  I fixed it up (see below) and can carry the fix as
necessary.
-- 
Cheers,
Stephen Rothwell                    sfr@xxxxxxxxxxxxxxxx

diff --cc arch/arm/mach-s3c64xx/common.c
index 8ae5b16,e3e75d1..0000000
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@@ -15,182 -13,21 +15,182 @@@
   */
  
  #include <linux/kernel.h>
 +#include <linux/init.h>
 +#include <linux/module.h>
  #include <linux/interrupt.h>
 +#include <linux/ioport.h>
- #include <linux/sysdev.h>
+ #include <linux/device.h>
 -#include <linux/gpio.h>
 -#include <linux/irq.h>
 +#include <linux/serial_core.h>
 +#include <linux/platform_device.h>
  #include <linux/io.h>
 +#include <linux/dma-mapping.h>
 +#include <linux/irq.h>
 +#include <linux/gpio.h>
  
 +#include <asm/mach/arch.h>
 +#include <asm/mach/map.h>
  #include <asm/hardware/vic.h>
  
 -#include <plat/regs-irqtype.h>
 +#include <mach/map.h>
 +#include <mach/hardware.h>
  #include <mach/regs-gpio.h>
 -#include <plat/gpio-cfg.h>
  
 -#include <mach/map.h>
  #include <plat/cpu.h>
 +#include <plat/clock.h>
 +#include <plat/devs.h>
  #include <plat/pm.h>
 +#include <plat/gpio-cfg.h>
 +#include <plat/irq-uart.h>
 +#include <plat/irq-vic-timer.h>
 +#include <plat/regs-irqtype.h>
 +#include <plat/regs-serial.h>
 +
 +#include "common.h"
 +
 +/* uart registration process */
 +
 +void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 +{
 +	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
 +}
 +
 +/* table of supported CPUs */
 +
 +static const char name_s3c6400[] = "S3C6400";
 +static const char name_s3c6410[] = "S3C6410";
 +
 +static struct cpu_table cpu_ids[] __initdata = {
 +	{
 +		.idcode		= S3C6400_CPU_ID,
 +		.idmask		= S3C64XX_CPU_MASK,
 +		.map_io		= s3c6400_map_io,
 +		.init_clocks	= s3c6400_init_clocks,
 +		.init_uarts	= s3c64xx_init_uarts,
 +		.init		= s3c6400_init,
 +		.name		= name_s3c6400,
 +	}, {
 +		.idcode		= S3C6410_CPU_ID,
 +		.idmask		= S3C64XX_CPU_MASK,
 +		.map_io		= s3c6410_map_io,
 +		.init_clocks	= s3c6410_init_clocks,
 +		.init_uarts	= s3c64xx_init_uarts,
 +		.init		= s3c6410_init,
 +		.name		= name_s3c6410,
 +	},
 +};
 +
 +/* minimal IO mapping */
 +
 +/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
 +#define UART_OFFS (S3C_PA_UART & 0xfffff)
 +
 +static struct map_desc s3c_iodesc[] __initdata = {
 +	{
 +		.virtual	= (unsigned long)S3C_VA_SYS,
 +		.pfn		= __phys_to_pfn(S3C64XX_PA_SYSCON),
 +		.length		= SZ_4K,
 +		.type		= MT_DEVICE,
 +	}, {
 +		.virtual	= (unsigned long)S3C_VA_MEM,
 +		.pfn		= __phys_to_pfn(S3C64XX_PA_SROM),
 +		.length		= SZ_4K,
 +		.type		= MT_DEVICE,
 +	}, {
 +		.virtual	= (unsigned long)(S3C_VA_UART + UART_OFFS),
 +		.pfn		= __phys_to_pfn(S3C_PA_UART),
 +		.length		= SZ_4K,
 +		.type		= MT_DEVICE,
 +	}, {
 +		.virtual	= (unsigned long)VA_VIC0,
 +		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC0),
 +		.length		= SZ_16K,
 +		.type		= MT_DEVICE,
 +	}, {
 +		.virtual	= (unsigned long)VA_VIC1,
 +		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC1),
 +		.length		= SZ_16K,
 +		.type		= MT_DEVICE,
 +	}, {
 +		.virtual	= (unsigned long)S3C_VA_TIMER,
 +		.pfn		= __phys_to_pfn(S3C_PA_TIMER),
 +		.length		= SZ_16K,
 +		.type		= MT_DEVICE,
 +	}, {
 +		.virtual	= (unsigned long)S3C64XX_VA_GPIO,
 +		.pfn		= __phys_to_pfn(S3C64XX_PA_GPIO),
 +		.length		= SZ_4K,
 +		.type		= MT_DEVICE,
 +	}, {
 +		.virtual	= (unsigned long)S3C64XX_VA_MODEM,
 +		.pfn		= __phys_to_pfn(S3C64XX_PA_MODEM),
 +		.length		= SZ_4K,
 +		.type		= MT_DEVICE,
 +	}, {
 +		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
 +		.pfn		= __phys_to_pfn(S3C64XX_PA_WATCHDOG),
 +		.length		= SZ_4K,
 +		.type		= MT_DEVICE,
 +	}, {
 +		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
 +		.pfn		= __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
 +		.length		= SZ_1K,
 +		.type		= MT_DEVICE,
 +	},
 +};
 +
 +struct sysdev_class s3c64xx_sysclass = {
 +	.name	= "s3c64xx-core",
 +};
 +
 +static struct sys_device s3c64xx_sysdev = {
 +	.cls	= &s3c64xx_sysclass,
 +};
 +
 +/* read cpu identification code */
 +
 +void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
 +{
 +	/* initialise the io descriptors we need for initialisation */
 +	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 +	iotable_init(mach_desc, size);
 +	init_consistent_dma_size(SZ_8M);
 +
 +	/* detect cpu id */
 +	s3c64xx_init_cpu();
 +
 +	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 +}
 +
 +static __init int s3c64xx_sysdev_init(void)
 +{
 +	sysdev_class_register(&s3c64xx_sysclass);
 +	return sysdev_register(&s3c64xx_sysdev);
 +}
 +core_initcall(s3c64xx_sysdev_init);
 +
 +/*
 + * setup the sources the vic should advertise resume
 + * for, even though it is not doing the wake
 + * (set_irq_wake needs to be valid)
 + */
 +#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
 +#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) |	\
 +			 1 << (IRQ_PENDN - IRQ_VIC1_BASE) |	\
 +			 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |	\
 +			 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |	\
 +			 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
 +
 +void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 +{
 +	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 +
 +	/* initialise the pair of VICs */
 +	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
 +	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
 +
 +	/* add the timer sub-irqs */
 +	s3c_init_vic_timer_irq(5, IRQ_TIMER0);
 +}
  
  #define eint_offset(irq)	((irq) - IRQ_EINT(0))
  #define eint_irq_to_bit(irq)	((u32)(1 << eint_offset(irq)))

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