[PATCH] x86: Resolving inconsistency with Intel processor manual

[Ajaykumar Hotchandani]

Following is from Notes of section 11.5.3 of Intel processor manual
available at http://www.intel.com/Assets/PDF/manual/325384.pdf:
For the Pentium 4 and Intel Xeon processors, after the sequence of
steps given above has been executed, the cache lines containing the
code between the end of the WBINVD instruction and before the
MTRRS have actually been disabled may be retained in the cache
hierarchy. Here, to remove code from the cache completely, a second
WBINVD instruction must be executed after the MTRRs have been
disabled.

This patch provides resolution for that.
Ideally, I will like to make changes only for Pentium 4 and Xeon processors.
But, I am not finding easier way to do it.
And, extra wbinvd() instruction does not hurt much for other processors.

Signed-off-by: Ajaykumar Hotchandani <ajaykumar.hotchandani@xxxxxxxxxx>
---
 arch/x86/kernel/cpu/mtrr/generic.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/mtrr/generic.c 
b/arch/x86/kernel/cpu/mtrr/generic.c
index a71efcdb..4cd9919 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -693,6 +693,7 @@ static void prepare_set(void) 
__acquires(set_atomicity_lock)

        /* Disable MTRRs, and set the default type to uncached */
        mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
+       wbinvd();
 }

 static void post_set(void) __releases(set_atomicity_lock)
--
1.7.5.1

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