RE: [PATCH v3 2/8] arm/tegra: prepare early init for multiple tegravariants

[Stephen Warren]

Peter De Schrijver wrote at Monday, November 07, 2011 7:20 AM:
> This patch splits the early init code in a common and a tegra20 specific part.
> L2 cache initialization is generalized and discovers the cache associativity
> at runtime. Also use arm_pm_restart instead of arm_arch_reset and reset the
> the system using the PMC reset feature rather then the CAR system reset.

> -static void __init tegra_init_cache(void)
...
> +	aux_ctrl = readl(p + L2X0_CACHE_TYPE);
> +	aux_ctrl = (aux_ctrl & 0x700) << (17-8);
> +	aux_ctrl |= 0x6C000001;

It might be slightly clearer here to write:

> +	aux_ctrl = 0x6C000001;
> +	cache_type = readl(p + L2X0_CACHE_TYPE);
> +	aux_ctrl |= (cache_type & 0x700) << (17-8);

So that the contents of the cache type register isn't assigned to something
named after an unrelated register.

-- 
nvpublic

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