Re: [patch 3/3] x86: cache_info: Kill the atomic allocation inamd_init_l3_cache()

[Borislav Petkov]

On Sun, Jul 24, 2011 at 12:13:38PM -0400, Thomas Gleixner wrote:
> > Let me test the patchset on Monday to verify there are no other subtle
> > interactions I haven't thought of right now.

Yep, patches look good and boot as a xen guest too.

While you're at it, can you please also apply the following one which
updates L3 size calculation on F15h?

Thanks.

--
From: Frank Arnold <frank.arnold@xxxxxxx>
Date: Wed, 18 May 2011 11:32:10 +0200
Subject: [PATCH] x86, AMD, cacheinfo: Update calculation of L3 cache indices

L3 subcaches 0 and 1 of AMD Family 15h CPUs can have a size of 2MB.
Update the calculation routine for the number of L3 indices to reflect
that.

Signed-off-by: Frank Arnold <frank.arnold@xxxxxxx>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 951820f..a3b0811 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -314,6 +314,12 @@ static void __cpuinit amd_calc_l3_indices(struct amd_northbridge *nb)
 	/* calculate subcache sizes */
 	l3->subcaches[0] = sc0 = !(val & BIT(0));
 	l3->subcaches[1] = sc1 = !(val & BIT(4));
+
+	if (boot_cpu_data.x86 == 0x15) {
+		l3->subcaches[0] = sc0 += !(val & BIT(1));
+		l3->subcaches[1] = sc1 += !(val & BIT(5));
+	}
+
 	l3->subcaches[2] = sc2 = !(val & BIT(8))  + !(val & BIT(9));
 	l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
 
-- 
1.7.6.134.gcf13f6


-- 
Regards/Gruss,
Boris.

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