Re: [PATCH 2/2] ARM: EXYNOS4: Add more registers to be saved andrestored for PM

[MyungJoo Ham]

On Mon, Jul 18, 2011 at 5:00 PM, Kukjin Kim <kgene.kim@xxxxxxxxxxx> wrote:
> MyungJoo Ham wrote:
>>
>> We need more registers to be saved and restored for PM of Exynos4210.
>> Otherwise, with additional drivers running, suspend-to-RAM fails to wake
>> up properly. This patch adds registers omitted in the initial PM
>> patches.
>>
>> Signed-off-by: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx>
>> Signed-off-by: Kyungmin Park <kyungmin.park@xxxxxxxxxxx>
>> ---
>> Âarch/arm/mach-exynos4/pm.c | Â 77
>> +++++++++++++++++++++++++++++++++++++++++++-
>> Â1 files changed, 76 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
>> index a103c13..24c9265 100644
>> --- a/arch/arm/mach-exynos4/pm.c
>> +++ b/arch/arm/mach-exynos4/pm.c
>> @@ -27,6 +27,8 @@
>> Â#include <plat/cpu.h>
>> Â#include <plat/pm.h>
>> Â#include <plat/pll.h>
>> +#include <plat/regs-srom.h>
>> +#include <plat/regs-timer.h>
>>
>> Â#include <mach/regs-irq.h>
>> Â#include <mach/regs-gpio.h>
>> @@ -60,14 +62,20 @@ static struct sleep_save exynos4_vpll_save[] = {
>>
>> Âstatic struct sleep_save exynos4_core_save[] = {
>> Â Â Â /* CMU side */
>> + Â Â SAVE_ITEM(S5P_CLKSRC_LEFTBUS),
>
> I think, the reset/default value(0x0, SCLKMPLL) has no problem.
>
>> + Â Â SAVE_ITEM(S5P_CLKOUT_CMU_LEFTBUS),
>
> This is for debugging? So I think no need this.
>
>> + Â Â SAVE_ITEM(S5P_CLKSRC_RIGHTBUS),
>
> Same as 'CLKSRC_LEFTBUS'
>
>> + Â Â SAVE_ITEM(S5P_CLKOUT_CMU_RIGHTBUS),
>
> Same as 'CMU_LEFTBUS'
>
>> + Â Â SAVE_ITEM(S5P_CLKOUT_CMU_TOP),
>
> For debugging...
>
>> + Â Â SAVE_ITEM(S5P_CLKOUT_CMU_DMC),
>
> Same as above.
>
> (snip)
>
>> + Â Â SAVE_ITEM(S5P_APLL_LOCK),
>> + Â Â SAVE_ITEM(S5P_MPLL_LOCK),
>> + Â Â SAVE_ITEM(S5P_APLL_CON0),
>> + Â Â SAVE_ITEM(S5P_APLL_CON1),
>> + Â Â SAVE_ITEM(S5P_MPLL_CON0),
>> + Â Â SAVE_ITEM(S5P_MPLL_CON1),
>
> Basically, these value should be set in boot-loader after wake up.
>
> (snip)
>
>> + Â Â /* PMU */
>> + Â Â SAVE_ITEM(S5P_HDMI_PHY_CONTROL),
>> + Â Â SAVE_ITEM(S5P_USBOTG_PHY_CONTROL),
>> + Â Â SAVE_ITEM(S5P_USBHOST_PHY_CONTROL),
>> + Â Â SAVE_ITEM(S5P_DAC_CONTROL),
>> + Â Â SAVE_ITEM(S5P_MIPI_CONTROL0),
>> + Â Â SAVE_ITEM(S5P_MIPI_CONTROL1),
>> + Â Â SAVE_ITEM(S5P_ADC_CONTROL),
>> + Â Â SAVE_ITEM(S5P_PCIE_CONTROL),
>> + Â Â SAVE_ITEM(S5P_SATA_CONTROL),
>> + Â Â SAVE_ITEM(S5P_PMU_DEBUG),
>> + Â Â SAVE_ITEM(S5P_ARM_CORE0_CONFIGURATION),
>> + Â Â SAVE_ITEM(S5P_ARM_CORE1_CONFIGURATION),
>> + Â Â SAVE_ITEM(S5P_ARM_CPU_L2_0_CONFIGURATION),
>> + Â Â SAVE_ITEM(S5P_ARM_CPU_L2_1_CONFIGURATION),
>> + Â Â SAVE_ITEM(S5P_XUSBXTI_CONFIGURATION),
>> + Â Â SAVE_ITEM(S5P_XXTI_CONFIGURATION),
>> + Â Â SAVE_ITEM(S5P_PMU_CAM_CONF),
>> + Â Â SAVE_ITEM(S5P_PMU_TV_CONF),
>> + Â Â SAVE_ITEM(S5P_PMU_MFC_CONF),
>> + Â Â SAVE_ITEM(S5P_PMU_G3D_CONF),
>> + Â Â SAVE_ITEM(S5P_PMU_LCD0_CONF),
>> + Â Â SAVE_ITEM(S5P_PMU_LCD1_CONF),
>> + Â Â SAVE_ITEM(S5P_MAUDIO_CONFIGURATION),
>> + Â Â SAVE_ITEM(S5P_PMU_GPS_CONF),
>
> Since PMU part is alive block, so no need.
>
>> +
>> + Â Â /* System Controller side */
>> + Â Â SAVE_ITEM(S3C_VA_SYS + 0x0210),
>> + Â Â SAVE_ITEM(S3C_VA_SYS + 0x0214),
>> + Â Â SAVE_ITEM(S3C_VA_SYS + 0x0218),
>> + Â Â SAVE_ITEM(S3C_VA_SYS + 0x0220),
>> + Â Â SAVE_ITEM(S3C_VA_SYS + 0x0230),
>
> Hmm..really need this?
>
>> +
>> Â Â Â /* GIC side */
>> Â Â Â SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
>> Â Â Â SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
>> @@ -232,11 +286,32 @@ static struct sleep_save exynos4_core_save[] = {
>> Â Â Â SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20),
>> Â Â Â SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24),
>>
>> -
>> Â Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
>> Â Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
>> Â Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
>> Â Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
>> + Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
>> + Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
>> + Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
>> + Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
>> + Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
>> + Â Â SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
>
> No need to save/restore external GIC part...
>
> (snip)
>
>> + Â Â /* PWM Register */
>> + Â Â SAVE_ITEM(S3C2410_TCFG0),
>> + Â Â SAVE_ITEM(S3C2410_TCFG1),
>> + Â Â SAVE_ITEM(S3C64XX_TINT_CSTAT),
>> + Â Â SAVE_ITEM(S3C2410_TCON),
>> + Â Â SAVE_ITEM(S3C2410_TCNTB(0)),
>> + Â Â SAVE_ITEM(S3C2410_TCMPB(0)),
>> + Â Â SAVE_ITEM(S3C2410_TCNTO(0)),
>
> PWM? I'm not sure why this is needed here.
>
> (snip)
>
> Others, ok.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@xxxxxxxxxxx>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
Hello,


Removing the registers you've mentioned didn't break the PM test as
NURI board also does not use debug clocks.

And, PWM driver appears to backup and restore ctirical register; thus,
we don't need to back them up at pm.c. That's good.

For PLLs, I'll let it rely on bootloader as you've mentioned.

The corrected patch will follow this reply soon.


Thanks.

- MyungJoo

-- 
MyungJoo Ham (íëì), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
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