Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASEMSR

[Suresh Siddha]

On Mon, 2011-07-11 at 22:59 -0700, Naga Chumbalkar wrote:
> If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
> MSR, let's preserve it.
> 
> The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2 
> in: http://www.intel.com/Assets/PDF/manual/318148.pdf).
> 
> Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@xxxxxx>
> Cc: Suresh Siddha <suresh.b.siddha@xxxxxxxxx>
> 
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index b9338b8..f7b0c7a 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -1429,7 +1429,7 @@ void enable_x2apic(void)
>  	rdmsr(MSR_IA32_APICBASE, msr, msr2);
>  	if (!(msr & X2APIC_ENABLE)) {
>  		printk_once(KERN_INFO "Enabling x2apic\n");
> -		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
> +		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
>  	}
>  }
>  #endif /* CONFIG_X86_X2APIC */

yeah, I don't think it was intentional.

Reviewed-by: Suresh Siddha <suresh.b.siddha@xxxxxxxxx>

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