Re: [PATCH 1/4] perf: Add memory load/store events generic code

[Peter Zijlstra]

On Mon, 2011-07-04 at 10:33 +0200, Peter Zijlstra wrote:
> On Mon, 2011-07-04 at 08:02 +0000, Lin Ming wrote:
> > +/*
> > + * Memory load operation info encoding
> > + */
> > +
> > +/* Bits(0-1) {L1, L2, L3, RAM} or {unknown, IO, uncached, reserved}
> > */
> > +#define MEM_LOAD_L1                    0x00
> > +#define MEM_LOAD_L2                    0x01
> > +#define MEM_LOAD_L3                    0x02
> > +#define MEM_LOAD_RAM                   0x03
> > +#define MEM_LOAD_UNKNOWN               0x00
> > +#define MEM_LOAD_IO                    0x01
> > +#define MEM_LOAD_UNCACHED              0x02
> > +#define MEM_LOAD_RESERVED              0x03
> > +
> > +/* Bits(2-3) {toggle, snoop, local, remote} */
> > +#define MEM_LOAD_TOGGLE                        (0x00 << 2)
> > +#define MEM_LOAD_SNOOP                 (0x01 << 2)
> > +#define MEM_LOAD_LOCAL                 (0x02 << 2)
> > +#define MEM_LOAD_REMOTE                        (0x03 << 2)
> > +
> > +/* Bits(4-5) {modified, exclusive, shared, invalid} */
> > +#define MEM_LOAD_MODIFIED              (0x00 << 4)
> > +#define MEM_LOAD_EXCLUSIVE             (0x01 << 4)
> > +#define MEM_LOAD_SHARED                        (0x02 << 4)
> > +#define MEM_LOAD_INVALID               (0x03 << 4) 
> 
> Did anybody check with the other PMUs that have similar features like
> PowerPC and possibly IA64?
> 
> I keep mentioning this, nobody seems interested.

Anton, Paulus, IIRC PowerPC had some sort of Data-Source indication,
would you have some docs available on the PowerPC PMU?
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