Re: re-enable Nehalem raw Offcore-Events support

[Andi Kleen]

> I would say that most if not all of the events are not generalizable
> in the sense that you are talking about; the events are very
> specific to the Torrent chip.  For example, the Torrent chip

It's similar also on Intel chips. There are lots of events 
which are useful, but are unlikely to have any equivalents
on other designs (or sometimes not even in later/earlier chip
generations). So such a requirement would make it impossible
to support them.

Given a lot of them are obscure, but a lot of others are not
and they can be very useful for specific analyses.
Computers are getting more and more complex and we need all
the help we can get to understand their behaviour.

For example we've been recently using various Nehalem+ events for NUMA
tuning (memory latency and offcore) and it is very useful and 
fuitful.  But there are a lot of specialities there which do not extend to 
other chips.

I've been working around that now by programming the special registers 
in user space from special wrapper scripts, but clearly that's not a good 
solution and doesn't also work in all cases.

-Andi
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