Re: [PATCH urgent] x86: Save cr4 to mmu_cr4_features at boot time

[H. Peter Anvin]

On 04/04/2011 11:43 PM, Rafael J. Wysocki wrote:
> On Tuesday, April 05, 2011, H. Peter Anvin wrote:
>> On 04/04/2011 11:29 PM, Rafael J. Wysocki wrote:
>>>>
>>>> Peter very consciously did not mark the fix for this commit as -stable 
>>>> material. It was ineligible for -stable for multiple reasons: it by no means 
>>>> fixed a 2.6.39 regression and the fix was literally just a few days old.
>>>
>>> Has this issue been resolved in the mainline, BTW?
>>>
>>
>> Just to refresh my memory... is this an issue in mainline, or is it only
>> a problem in the backport (I'm wondering if the trampoline unification
>> patches might have accidentally solved the issue)?
> 
> 
> The problem is in mainline too, please fix ASAP.
> 

For the suspend/resume case this seems like the sanest way to fix it in
my opinion.  However, I am a bit concerned since I'm still not sure
we're programming registers in the correct order, that is:

MISC_ENABLE -> EFER -> cr4 -> cr3 -> cr0

I will look at this issue later this evening, but I wanted your opinion
on it.

	-hpa
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index 87bb35e..69dbf42 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -98,13 +98,12 @@ static void __save_processor_state(struct saved_context *ctxt)
 	ctxt->cr0 = read_cr0();
 	ctxt->cr2 = read_cr2();
 	ctxt->cr3 = read_cr3();
-#ifdef CONFIG_X86_32
 	ctxt->cr4 = read_cr4_safe();
-#else
-/* CONFIG_X86_64 */
-	ctxt->cr4 = read_cr4();
+	mmu_cr4_features = ctxt->cr4;
+#ifdef CONFIG_X86_64
 	ctxt->cr8 = read_cr8();
 #endif
+
 	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
 					       &ctxt->misc_enable);
 }