RE: Interrupt Latencies

[Schaefer Dr, Frank-Rene ()]

In response to Thomas Gleixner:

> Interrupt latency depends on various factors:
> 
>   - Interrupt disabled code regions
Could you tell us how this could be detected or measured?
Is there a central place, where we could toggle a pin to 
see when interrupts are enabled/disabled? 

>   - Concurrent interrupts and the ordering of handling
We are only considering the best times that we measure.
The only other interrupts are SATA and system timer, I guess.

>   - Deep idle states
You mean 'suspend' or some type of CPU sleep. Could you elaborate?
We do not suspend. This should also only be the case for the 
first chunk that is transmitted. But the latencies remain
over longer time spans.

>   - Bus contention
Nothing else is running. 

>   - Cache misses
We cannot make any statements about that. But, we are **not** 
working on huge data or code regions.

> >
> >       pin IN        .-------------------------
> >       ______________|
> >
> >       pin OUT                     .-----------
> >       ____________________________|
> >
> >                     |<- latency ->|
> >

> How is that interrupt connected to the CPU/chipset? 
The port is part of the chipset connected internally 
via PCI.

> Which driver(s) is/are involved ? 
http://lxr.free-electrons.com/source/drivers/gpio/pl061.c

> How is the pin OUT accessed from the driver?
gpio_set_value(Pin, Value);

we measured the delay and could find that it was in the range
of some nano seconds.

Best Regards

Frank Schäfer and Joachim Becker.

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