Re: [PATCH 5/5] perf, x86: Add support for AMD family 15h core counters

[Stephane Eranian]

On Wed, Feb 2, 2011 at 6:29 PM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> On Wed, 2011-02-02 at 18:24 +0100, Robert Richter wrote:
>> On 02.02.11 12:03:18, Peter Zijlstra wrote:
>> > On Wed, 2011-02-02 at 17:41 +0100, Robert Richter wrote:
>> > > +    unsigned int  Âeventsel;
>> > > +    unsigned int  Âperfctr;
>> > > +    unsigned int  Â*eventsel_map;
>> > > +    unsigned int  Â*perfctr_map;
>> > > Â Â Â Â u64 Â Â Â Â Â Â (*event_map)(int);
>> > >     int       max_events;
>> > >     int       num_counters;
>> > > @@ -323,11 +325,17 @@ again:
>> > >
>> > > Âstatic inline unsigned int x86_pmu_config_addr(int index)
>> > > Â{
>> > > + Â Â Â if (x86_pmu.eventsel_map)
>> > > + Â Â Â Â Â Â Â return x86_pmu.eventsel_map[index];
>> > > +
>> > > Â Â Â Â return x86_pmu.eventsel + index;
>> > > Â}
>> > >
>> > > Âstatic inline unsigned int x86_pmu_event_addr(int index)
>> > > Â{
>> > > + Â Â Â if (x86_pmu.perfctr_map)
>> > > + Â Â Â Â Â Â Â return x86_pmu.perfctr_map[index];
>> > > +
>> > > Â Â Â Â return x86_pmu.perfctr + index;
>> > > Â}
>> >
>> > Why this and not something like x86_pmu.perfctr + (index << 1)?
>> > You could even use alternatives.
>>
>> I was thinking about this. The main reason is the implementation of
>> northbridge counters, the range is in MSRC001_02[47:40]. This would
>> add more complexity then. Using a table would be something like
>>
>> unsigned int eventsel_f15h[] = {
>> Â Â Â MSR_F15H_PERF_CTL,
>> Â Â Â MSR_F15H_PERF_CTL + 2,
>> Â Â Â MSR_F15H_PERF_CTL + 4,
>> Â Â Â MSR_F15H_PERF_CTL + 6,
>> Â Â Â MSR_F15H_PERF_CTL + 8,
>> Â Â Â MSR_F15H_PERF_CTL + 10,
>> Â Â Â MSR_F15H_NB_PERF_CTL,
>> Â Â Â MSR_F15H_NB_PERF_CTL + 2,
>> Â Â Â MSR_F15H_NB_PERF_CTL + 6,
>> Â Â Â MSR_F15H_NB_PERF_CTL + 8,
>> };
>>
>> We don't need to change the address generation for this. Otherwise we
>> need to introduce more logic for the calculation.
>>
>> Also, were could be potential easier implementations for fixed
>> counters, BTS, P4, IBS, etc. But didn't look that close at it.
>>
>> (Btw, I am not yet sure if NB counters shouldn't better start at index
>> 16 or so to reserve space for perf counter expansion.)
>
> Now that the NB PMU is completely separate from the core PMU, wouldn't
> it make more sense to implement that as a separate entity just like the
> intel uncore bits?

I agree on this.
>
>
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