Re: [PATCH v3 1/1] USB: cns3xxx: Add EHCI and OHCI bus glue for cns3xxxSOCs

From: David Daney
Date: Mon Nov 29 2010 - 14:23:37 EST


On 11/25/2010 07:58 AM, mkl0301@xxxxxxxxx wrote:
From: Mac Lin<mkl0301@xxxxxxxxx>

The CNS3XXX SOC has include USB EHCI and OHCI compatible controllers. This
patch adds the necessary glue logic to allow ehci-hcd and ohci-hcd drivers to
work on CNS3XXX

The EHCI and OHCI controllers share a common clock control and reset bit,
therefore additional check for the timming of enabling and disabling is
required. The USB bit of PLL Power Down Control is also shared by OTG, 24MHz
UART clock, Crypto clock, PCIe reference clock, and Clock Scale Generator.
Therefore we only ensure it is enabled, while not disabling it.

Signed-off-by: Mac Lin<mkl0301@xxxxxxxxx>
---
drivers/usb/Kconfig | 2 +
drivers/usb/host/Kconfig | 15 ++++
drivers/usb/host/ehci-cns3xxx.c | 171 +++++++++++++++++++++++++++++++++++++++
drivers/usb/host/ehci-hcd.c | 5 +
drivers/usb/host/ohci-cns3xxx.c | 165 +++++++++++++++++++++++++++++++++++++
drivers/usb/host/ohci-hcd.c | 5 +
6 files changed, 363 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/host/ehci-cns3xxx.c
create mode 100644 drivers/usb/host/ohci-cns3xxx.c

diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 67eb377..5a7c8f1 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -41,6 +41,7 @@ config USB_ARCH_HAS_OHCI
default y if MFD_TC6393XB
default y if ARCH_W90X900
default y if ARCH_DAVINCI_DA8XX
+ default y if ARCH_CNS3XXX
# PPC:
default y if STB03xxx
default y if PPC_MPC52xx
@@ -66,6 +67,7 @@ config USB_ARCH_HAS_EHCI
default y if ARCH_AT91SAM9G45
default y if ARCH_MXC
default y if ARCH_OMAP3
+ default y if ARCH_CNS3XXX
default PCI


Can these be moved to the archecture Kconfig as:

select USB_ARCH_HAS_OHCI
select USB_ARCH_HAS_EHCI

Well to answer my own question, yes they can.

Should they? I think so.

David Daney
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