Re: [rfc 1/3] perf, x86: P4 PMU - describe config format

[Stephane Eranian]

On Fri, Nov 26, 2010 at 1:59 PM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> On Fri, 2010-11-26 at 13:48 +0100, Stephane Eranian wrote:
>> Reviewed-by: Stephane Eranian <eranian@xxxxxxxxxx>
>
> The new one, right? The one that reads:
>
Yes. Sorry about that.

> + * Â ÂLow 32 bits
> + * Â Â-----------
> + * Â Â Â0-6: P4_PEBS_METRIC enum
> + * Â Â 7-11: Â Â Â Â Â Â Â Â Â Âreserved
> + * Â Â Â 12: Â Â Â Â Â Â Â Â Â Âreserved (Enable)
> + * Â Â13-15: Â Â Â Â Â Â Â Â Â Âreserved (ESCR select)
> + * Â Â16-17: Active Thread
> + * Â Â Â 18: Compare
> + * Â Â Â 19: Complement
> + * Â Â20-23: Threshold
> + * Â Â Â 24: Edge
> + * Â Â Â 25: Â Â Â Â Â Â Â Â Â Âreserved (FORCE_OVF)
> + * Â Â Â 26: Â Â Â Â Â Â Â Â Â Âreserved (OVF_PMI_T0)
> + * Â Â Â 27: Â Â Â Â Â Â Â Â Â Âreserved (OVF_PMI_T1)
> + * Â Â28-29: Â Â Â Â Â Â Â Â Â Âreserved
> + * Â Â Â 30: Â Â Â Â Â Â Â Â Â Âreserved (Cascade)
> + * Â Â Â 31: Â Â Â Â Â Â Â Â Â Âreserved (OVF)
> + *
> + * Â ÂHigh 32 bits
> + * Â Â------------
> + * Â Â Â Â0: Â Â Â Â Â Â Â Â Â Âreserved (T1_USR)
> + * Â Â Â Â1: Â Â Â Â Â Â Â Â Â Âreserved (T1_OS)
> + * Â Â Â Â2: Â Â Â Â Â Â Â Â Â Âreserved (T0_USR)
> + * Â Â Â Â3: Â Â Â Â Â Â Â Â Â Âreserved (T0_OS)
> + * Â Â Â Â4: Tag Enable
> + * Â Â Â5-8: Tag Value
> + * Â Â 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
> + * Â Â25-30: enum P4_EVENTS
> + * Â Â Â 31: Â Â Â Â Â Â Â Â Â Âreserved (HT thread)
>
>
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