Re: [rfc 1/3] perf, x86: P4 PMU - describe config format

[Stephane Eranian]

On Tue, Nov 23, 2010 at 11:46 PM, Cyrill Gorcunov <gorcunov@xxxxxxxxxx> wrote:
> Add description of .config in a sake of RAW events.
> At least this should bring some light to those who
> will be reading this code.
>
> Signed-off-by: Cyrill Gorcunov <gorcunov@xxxxxxxxxx>
> CC: Lin Ming <ming.m.lin@xxxxxxxxx>
> CC: Stephane Eranian <eranian@xxxxxxxxxx>
> CC: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
> ---
> Âarch/x86/include/asm/perf_event_p4.h | Â 62 ++++++++++++++++++++++++++++++-----
> Â1 file changed, 54 insertions(+), 8 deletions(-)
>
> Index: linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
> =====================================================================
> --- linux-2.6.git.orig/arch/x86/include/asm/perf_event_p4.h
> +++ linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
> @@ -744,14 +744,6 @@ enum P4_ESCR_EMASKS {
> Â};
>
> Â/*
> - * P4 PEBS specifics (Replay Event only)
> - *
> - * Format (bits):
> - * Â 0-6: metric from P4_PEBS_METRIC enum
> - * Â Â7 : reserved
> - * Â Â8 : reserved
> - * 9-11 : reserved
> - *
> Â* Note we have UOP and PEBS bits reserved for now
> Â* just in case if we will need them once
> Â*/
> @@ -788,5 +780,59 @@ enum P4_PEBS_METRIC {
> Â Â Â ÂP4_PEBS_METRIC__max
> Â};
>
> +/*
> + * Notes on internal configuration of ESCR+CCCR tuples
> + *
> + * Since P4 has quite the different architecture of
> + * performance registers in compare with "architectural"
> + * once and we have on 64 bits to keep configuration
> + * of performance event, the following trick is used.
> + *
> + * 1) Since both ESCR and CCCR registers have only low
> + * Â Â32 bits valuable, we pack them into a single 64 bit
> + * Â Âconfiguration. Low 32 bits of such config correspond
> + * Â Âto low 32 bits of CCCR register and high 32 bits
> + * Â Âcorrespond to low 32 bits of ESCR register.
> + *
> + * 2) The meaning of every bit of such config field can
> + * Â Âbe found in Intel SDM but it should be noted that
> + * Â Âwe "borrow" some reserved bits for own usage and
> + * Â Âclean them or set to a proper value when we do
> + * Â Âa real write to hardware registers.
> + *
> + * 3) The format of bits of config is the following
> + * Â Âand should be either 0 or set to some predefined
> + * Â Âvalues:
> + *
> + * Â ÂLow 32 bits
> + * Â Â-----------
> + * Â Â Â0-6: P4_PEBS_METRIC enum
> + * Â Â 7-11: Â Â Â Â Â Â Â Â Â Âreserved
> + * Â Â Â 12: Active thread

I don't understand bit 12. In the actual register, it
corresponds to the enable bit. Seems you're overriding
its usage. Do I interpret this as saying: 0 = enable when
running on thread0, 1=monitoring when running on thread1?
And if I don't care?



> + * Â Â13-15: Â Â Â Â Â Â Â Â Â Âreserved (ESCR select)
> + * Â Â16-17: Compare
> + * Â Â Â 18: Complement
> + * Â Â20-23: Threshold
> + * Â Â Â 24: Edge
> + * Â Â Â 25: Â Â Â Â Â Â Â Â Â Âreserved (FORCE_OVF)
> + * Â Â Â 26: Â Â Â Â Â Â Â Â Â Âreserved (OVF_PMI_T0)
> + * Â Â Â 27: Â Â Â Â Â Â Â Â Â Âreserved (OVF_PMI_T1)
> + * Â Â28-29: Â Â Â Â Â Â Â Â Â Âreserved
> + * Â Â Â 30: Â Â Â Â Â Â Â Â Â Âreserved (Cascade)
> + * Â Â Â 31: Â Â Â Â Â Â Â Â Â Âreserved (OVF)
> + *
> + * Â ÂHigh 32 bits
> + * Â Â------------
> + * Â Â Â Â0: Â Â Â Â Â Â Â Â Â Âreserved (T1_USR)
> + * Â Â Â Â1: Â Â Â Â Â Â Â Â Â Âreserved (T1_OS)
> + * Â Â Â Â2: Â Â Â Â Â Â Â Â Â Âreserved (T0_USR)
> + * Â Â Â Â3: Â Â Â Â Â Â Â Â Â Âreserved (T0_OS)
> + * Â Â Â Â4: Tag Enable
> + * Â Â Â5-8: Tag Value
> + * Â Â 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
> + * Â Â25-30: enum P4_EVENTS
> + * Â Â Â 31: Â Â Â Â Â Â Â Â Â Âreserved (HT thread)
> + */
> +
> Â#endif /* PERF_EVENT_P4_H */
>
>
>
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