Re: [PATCH 4/4] [x86] perf: fix accidentally ack'ing a second eventon intel perf counter

[Stephane Eranian]

Don,

On Thu, Sep 2, 2010 at 4:19 PM, Don Zickus <dzickus@xxxxxxxxxx> wrote:
> On Thu, Sep 02, 2010 at 10:13:19AM +0200, Stephane Eranian wrote:
>> Robert,
>>
>> Do you have the test program you used to test this?
>> I believe the NHM hack does not solve the problem, it
>> just makes it harder to appear.
>
> Could be.
>
>>
>> I suspect the real issue is that the GLOBAL_STATUS
>> bitmask cannot be trusted. I'd like to verify this.
>>
>> Has the problem appear only on Nehalem or also on
>> Westmere?
>
> I was able to duplicate on
>
> Intel(R) Core(TM) i5 CPU Â Â Â Â 650 Â@ 3.20GHz
> Intel(R) Xeon(R) CPU Â Â Â Â Â X5560 Â@ 2.80GHz
>
I managed to reproduce on core i7 860 (without patch4).
Looking at the code again, I am dubious you ever execute
the retry goto. If the PMU is disabled and you've just
cleared the OVF_STAT, then I don't see where the new
overflows would come from. But that's a separate problem.

One thing I did is to compare status obtained via OVFL_STATUS
with one that I build manually by inspecting each individual
counter. The two returned bitmasks should always be identical
(with PEBS disabled).  When I got the spurious NMI, it did not
trip my status validation. So the OVFL_STATUS is valid.

I found something else that looked fishy. I am experimenting
with it. I will report back.


> with just running 'perf top' for about 60 seconds.
>
> You would need the first three patches to expose the problem.
>
> Reading the code, it seemed like the perf counters should be disabled and
> this patch should be unecessary, but after playing around with the code
> for a few hours, I came up with this patch to trap the issue.
>
> I read through the cpu errata and could not find anything related but I
> might have missed something.
>
> I am willing to help test if you have a more targeted patch.
>
Thanks.
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