Re: perf failed with kernel 2.6.35-rc

[Stephane Eranian]

On Tue, Jul 13, 2010 at 10:14 AM, Zhang, Yanmin
<yanmin_zhang@xxxxxxxxxxxxxxx> wrote:
> Peter,
>
> perf doesn't work on my Nehalem EX machine.
> 1) The 1st start of 'perf top' is ok;
> 2) Kill the 1st perf and restart it. It doesn't work. No data is showed.
>
> I located below commit:
> commit 1ac62cfff252fb668405ef3398a1fa7f4a0d6d15
> Author: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
> Date: Â Fri Mar 26 14:08:44 2010 +0100
>
> Â Âperf, x86: Add Nehelem PMU programming errata workaround
>
> Â Âworkaround From: Peter Zijlstra <a.p.zijlstra@xxxxxxxxx>
> Â ÂDate: Fri Mar 26 13:59:41 CET 2010
>
> Â ÂImplement the workaround for Intel Errata AAK100 and AAP53.
>
> Â ÂAlso, remove the Core-i7 name for Nehalem events since there are
> Â Âalso Westmere based i7 chips.
>
>
> If I comment out the workaround in function intel_pmu_nhm_enable_all,
> perf could work.
>
> A quick glance shows:
> wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x3);
> should be:
> wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x7);
>
>
> I triggered sysrq to dump PMU registers and found the last bit of
> global status register is 1. I added a status reset operation like below patch:
>
What do you call the last bit? bit0 or bit63?

> --- linux-2.6.35-rc5/arch/x86/kernel/cpu/perf_event_intel.c   2010-07-14 09:38:11.000000000 +0800
> +++ linux-2.6.35-rc5_fork/arch/x86/kernel/cpu/perf_event_intel.c    Â2010-07-14 14:41:42.000000000 +0800
> @@ -505,8 +505,13 @@ static void intel_pmu_nhm_enable_all(int
> Â Â Â Â Â Â Â Âwrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + 1, 0x4300B1);
> Â Â Â Â Â Â Â Âwrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + 2, 0x4300B5);
>
> - Â Â Â Â Â Â Â wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x3);
> + Â Â Â Â Â Â Â wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x7);
> Â Â Â Â Â Â Â Âwrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
> + Â Â Â Â Â Â Â /*
> + Â Â Â Â Â Â Â Â* Reset the last 3 bits of global status register in case
> + Â Â Â Â Â Â Â Â* previous enabling causes overflows.
> + Â Â Â Â Â Â Â Â*/

The workaround cannot cause on overflow because the associated counters
won't count anything given their umask value is 0 (which does not correspond
to anything for event 0xB1, event 0xB5 is undocumented). This is for the events
described in table A.2. If NHM-EX has a different definition for 0xB1, 0xB5,
then that's another story.


> + Â Â Â Â Â Â Â wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0x7);
>
> Â Â Â Â Â Â Â Âfor (i = 0; i < 3; i++) {
> Â Â Â Â Â Â Â Â Â Â Â Âstruct perf_event *event = cpuc->events[i];
>
>
>
> However, it still doesn't work. Current right way is to comment out
> the workaround.
>
> Yanmin
>
>
>
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