Re: [PATCH] x86/sfi: fix ioapic gsi range

[jacob pan]

Jacob Pan Mon,  7 Jun 2010 16:07:24 -0700
>SFI based platforms should have zero based gsi_base for IOAPICs found in SFI
>tables. The current code sets gsi_base starting from 1 when registering ioapic.
>The result is that Moorestown platform would have wrong mp_gsi_routing for each
>ioapic.
>
>Background:
>In Moorestown/Medfield platforms, there is no legacy IRQs, all gsis and irqs
>are one to one mapped, including those < 16. Specifically, IRQ0 and IRQ1 are
>used for per-cpu timers. So without this patch, IOAPIC pin to IRQ mapping is
>off by one.
>
Clarifiction/correction about IRQ0,1. I refer to IOAPIC IRQ #, which is the
IOAPIC RTE entry #. Not in the sense of kernel IRQ# which can be assigned
differently on Moorestown.
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