diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 95962a9..514692c 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -302,17 +302,20 @@ struct _cache_attr {
 };
 
 #ifdef CONFIG_CPU_SUP_AMD
-static unsigned int __cpuinit amd_calc_l3_indices(void)
+static int __cpuinit amd_calc_l3_indices(void)
 {
 	/*
 	 * We're called over smp_call_function_single() and therefore
 	 * are on the correct cpu.
 	 */
+	unsigned int sc0, sc1, sc2, sc3;
+	u32 val = 0;
 	int cpu = smp_processor_id();
 	int node = cpu_to_node(cpu);
 	struct pci_dev *dev = node_to_k8_nb_misc(node);
-	unsigned int sc0, sc1, sc2, sc3;
-	u32 val = 0;
+
+	if (!dev)
+		return -1;
 
 	pci_read_config_dword(dev, 0x1C4, &val);
 
@@ -328,24 +331,17 @@ static unsigned int __cpuinit amd_calc_l3_indices(void)
 static void __cpuinit
 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
 {
-	if (index < 3)
-		return;
+	int indices;
 
-	if (boot_cpu_data.x86 == 0x11)
-		return;
-
-	/* see errata #382 and #388 */
-	if ((boot_cpu_data.x86 == 0x10) &&
-	    ((boot_cpu_data.x86_model < 0x8) ||
-	     (boot_cpu_data.x86_mask  < 0x1)))
+	if (index < 3)
 		return;
 
-	/* not in virtualized environments */
-	if (num_k8_northbridges == 0)
+	indices = amd_calc_l3_indices();
+	if (indices < 0)
 		return;
 
 	this_leaf->can_disable = true;
-	this_leaf->l3_indices  = amd_calc_l3_indices();
+	this_leaf->l3_indices  = indices;
 }
 
 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,