Re: [PATCH 11/12] perf, x86: implement AMD IBS event configuration

[Stephane Eranian]

Robert,

Some more comments about model_spec.

> Except for the sample period IBS can only be set up with raw (model
> specific) config values and raw data samples. The event attributes for
> the syscall should be programmed like this (IBS_FETCH):
>
> Â Â Â Âmemset(&attr, 0, sizeof(attr));
>    Âattr.type    Â= PERF_TYPE_RAW;
> Â Â Â Âattr.sample_type = PERF_SAMPLE_CPU | PERF_SAMPLE_RAW;
>    Âattr.config   Â= IBS_FETCH_CONFIG_DEFAULT
>    Âattr.config   |=
> Â Â Â Â Â Â Â Â((unsigned long long)MODEL_SPEC_TYPE_IBS_FETCH << 32)
> Â Â Â Â Â Â Â Â& MODEL_SPEC_TYPE_MASK;
> Â Â Â Âattr.model_spec Â= 1;
>
Why do you need model_spec, in addition to your special encoding?

> Â/*
> + * Model specific hardware events
> + *
> + * With the attr.model_spec bit set we can setup hardware events
> + * others than generic performance counters. A special PMU 64 bit
> + * config value can be passed through the perf_event interface. The
> + * concept of PMU model-specific arguments was practiced already in
> + * Perfmon2. The type of event (8 bits) is determinded from the config
> + * value too, bit 32-39 are reserved for this.
> + */
Isn't the config field big enough to encode all the information you need?
In the kernel, you could check bit 32-39 and based on host CPU determine
whether it refers to IBS or is a bogus value. I am trying to figure out what
model_spec buys you. I believe RAW does not mean the final value as
accepted by HW but a value that must be interpreted by the model-specific
code to eventually come up with a raw HW value. In the current code, the
RAW value is never passed as is, it is assembled from various bits and
pieces incl. attr.config of course.
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